Auflistung Nach Schlagwort "Timing Analysis"
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A Fast Timing Separation of Events Algorithm for Concurrent Systems
(2019)In this work, we present a fast, polynomial time implementation of the Timing Separation of Events (TSE) Algorithm, with complexity O(E × (V+E). TSE computation is a fundamental problem in the analysis of event-driven, ... -
Instruction-based timing analysis in pipelined processors
(2019)Traditional timing analysis techniques for microprocessor design are based on the static analysis approach, in which clock frequency is set in accord with the worst-case delay in the processor circuit operation, regardless ... -
Instruction-Flow-Based Timing Analysis in Pipelined Processors
(2019)Microprocessor design utilizes timing analysis in order to establish the maximal operation clock speed of the circuit. In static timing analysis, clock frequency is set in accord with the worst-case delay in the circuit ... -
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
(2022)With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ... -
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis
(2022)Traditional processor architectures utilize an external DRAM for data storage, while they also operate under worst-case timing constraints. Such designs are heavily constrained by the delay costs of the data transfer between ... -
On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron Technologies
(2021)Soft errors constitute a crucial reliability concern for the Integrated Circuits (ICs) as the continuous CMOS technology downscaling renders them vulnerable to radiation-induced hazards. Therefore, the Soft Error Rate (SER) ... -
A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects
(2019)Signoff timing analysis is essential in order to verify the proper operation of VLSI circuits. As process technologies scale down towards nanometer regimes, the fast and accurate timing analysis of interconnects has become ... -
TKtimer: Fast & accurate clock network pessimism removal
(2015)As integrated circuit process technology progresses into the deep sub-micron region, the phenomenon of process variation has a growing impact on the design and analysis of digital circuits and more specifically in the ...