Πλοήγηση ανά Θέμα "System level simulation"
Αποτελέσματα 1-3 από 3
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High-speed optical cache memory as single-level shared cache in chip-multiprocessor architectures
(2015)We present an optical bus-based Chip Multiprocessor architecture where the processing cores share an optical single-level cache unit. Physically, the optical cache is implemented externally in a separate chip located next ... -
A novel chip-multiprocessor architecture with optically interconnected shared L1 optical cache memory
(2014)We demonstrate a system-level CMP architecture where optical cache memories are shared among multiple processing cores through optical buses. System-level simulations show 25-45% execution time improvement and significant ... -
An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memory
(2016)We present an optical bus-based chip-multiprocessor architecture where the processing cores share an optical single-level cache implemented in a separate chip next to the Central-Processing-Unit (CPU) die. The interconnection ...