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Parcourir par sujet "Standard-cell placement"

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    • Domocus: Lock free parallel legalization in standard cell placement 

      Oikonomou P., Koziri M.G., Dadaliaris A.N., Loukopoulos T., Stamoulis G.I. (2017)
      In the cell placement problem a circuit's cells must be placed within a specified chip area so that they are row aligned and contain no overlaps. The problem is usually tackled in phases, whereby in the first phase a global ...

    • Enhanced tetris legalization 

      Dadaliaris A.N., Nerantzaki E., Oikonomou P., Hatzaras Y., Troumpoulou A.-O., Arvanitakis I., Stamoulis G.I. (2016)
      Legalization and detailed placement methods for standard cell designs, are two of the most notable topics in current VLSI research. Being the final steps in a classic placement procedure they must be efficient in terms of ...

    • Exploiting Net Connectivity in Legalization and Detailed Placement Scenarios 

      Dadaliaris A., Kranas G., Oikonomou P., Floros G., Dossis M. (2022)
      Standard-cell placement is the fundamental step in a typical VLSI/ASIC design flow. Its result, paired with the outcome of the routing procedure can be the decisive factor in rendering a design manufacturable. Global ...

    • Performance evaluation of tetris-based legalization heuristics 

      Dadaliaris A.N., Oikonomou P., Nerantzaki E., Loukopoulos T., Koziri M.G., Stamoulis G.I. (2016)
      Algorithms for standard cell placement legalization have attracted significant research efforts in the past. A prominent member of this category is the Tetris algorithm which is a simple and particularly fast method for ...

    • PyPUT: Python-based Placement Utilities Toolset 

      Kranas G., Tsalamagkakis G.-C., Oikonomou P., Dadaliaris A.N. (2018)
      In the placement stage of a standard-cell design flow, a set of cells must be placed within a specified rectangular region, that may contain obstacles, in such a way that overlaps and overflows are non-existent and a target ...

    • SCIZER: A scalable placement visualizer/analyzer 

      Dadaliaris A.N., Oikonomou P., Koziri M.G., Hatzaras Y., Stamoulis G.I. (2017)
      The major design challenges of ASIC design, like power dissipation, timing, voltage-drop, interconnect and reliability are tackled during the Physical Design phase of any flow. The placement procedure can significantly ...

    • A Tetris-based legalization heuristic for standard cell placement with obstacles 

      Oikonomou P., Dadaliaris A.N., Loukopoulos T., Kakarountas A., Stamoulis G.I. (2018)
      Legalization techniques are used both as a final stage and potentially as part of an iterative process of a global cell placement algorithm that distributes cells over a chip area in order to optimize criteria such as ...