Πλοήγηση ανά Θέμα "Radiation hardening"
Αποτελέσματα 1-11 από 11
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A Layout-Based Soft Error Rate Estimation and Mitigation in the Presence of Multiple Transient Faults in Combinational Logic
(2020)Cosmic radiation resulting in transient faults to the combinational logic of Integrated Circuits (ICs), constitutes a major reliability concern for space applications. In addition, continuous technology shrinking allows ... -
Multiple Transient Faults in Combinational Logic with Placement Considerations
(2019)Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the ... -
On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron Technologies
(2021)Soft errors constitute a crucial reliability concern for the Integrated Circuits (ICs) as the continuous CMOS technology downscaling renders them vulnerable to radiation-induced hazards. Therefore, the Soft Error Rate (SER) ... -
A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology
(2019)A considerable disadvantage that comes with the downscaling of the CMOS technology is the ever-increasing susceptibility of Integrated Circuits (ICs) to soft errors. Therefore, the study of the radiation-induced transient ... -
Placement-based SER estimation in the presence of multiple faults in combinational logic
(2017)Susceptibility of modern ICs to radiation-induced faults constitutes a matter of great concern in the recent years. Particularly, the transient faults and their impact on the combinational logic remain an intriguing issue, ... -
R-Abax: A radiation hardening legalisation algorithm satisfying TMR spacing constraints
(2020)Faults caused by ionising radiation have become a significant reliability issue in modern ICs. However, the Radiation Hardening (RADHARD) design flow differs from the standard design flow. Thus, there is not sufficient ... -
Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL
(2020)Reduction in device feature sizes and supply voltage renders modern Integrated Circuits (ICs) more susceptible to Soft Errors (SEs), i.e. Transient Faults caused by ionising radiation. Moreover, the RADiation HARDening ... -
RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening
(2022)The manufacturing of modern Integrated Circuits (ICs), resistant against faults caused by ionising radiation, has become quite challenging due to the rapid advancement of VLSI technology. Additionally, the Radiation Hardening ... -
RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraints
(2021)The continuous evolution of VLSI technology as well as the device shrinking render the Integrated Circuits more susceptible to hazards caused by ionising radiation, as Soft Errors. Moreover, the Radiation Hardening process, ... -
SER analysis of multiple transient faults in combinational logic
(2016)In the VLSI field, reliability of chips is a major issue and it becomes more significant considering the continuous technology down-scaling. Modern chips are extremely sensitive to various factors such as radiation and, ... -
Single Event Transients Generation and Propagation Flow using Commercial EDA Tools
(2021)The ever increasing demand for reliable microelectronic systems in the presence of radiation, combined with the continuous shrinking of CMOS technologies, has rendered the impact of radiation-induced voltage glitches, known ...