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Πλοήγηση ανά Θέμα "High level synthesis"

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    • Compiler transformations in hardware synthesis of Mpeg2 codes 

      Chatzianastasiou G., Tsakyridis A., Dimitriou G., Stamoulis G., Dossis M. (2016)
      High-level synthesis is the technique that translates high-level programming language programs into equivalent hardware descriptions. The use of conventional programming languages as input to high-level synthesis is ...

    • Design Space Exploration of a Sparse MobileNetV2 Using High-Level Synthesis and Sparse Matrix Techniques on FPGAs 

      Tragoudaras A., Stoikos P., Fanaras K., Tziouvaras A., Floros G., Dimitriou G., Kolomvatsos K., Stamoulis G. (2022)
      Convolution Neural Networks (CNNs) are gaining ground in deep learning and Artificial Intelligence (AI) domains, and they can benefit from rapid prototyping in order to produce efficient and low-power hardware designs. The ...

    • Global and Pointer Variables in High-Level Synthesis 

      Dimitriou G., Dossis M., Stamoulis G. (2020)
      High-level synthesis (HLS) has been an important tool in digital circuit design for more than two decades, especially for processor components like accelerators or coprocessors. However, many high-level language characteristics ...

    • Hardware synthesis of high-level C constructs 

      Dossis M., Dimitriou G. (2015)
      In this paper, experiments with a useable C frontend for the CCC behavioural synthesis tools are presented and analysed. This tool combination is able to rapidly deliver provably-correct hardware implementations at the RTL ...

    • High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs 

      Tariq O.B., Shan J., Floros G., Sotiriou C.P., Casu M.R., Lazarescu M.T., Lavagno L. (2021)
      Ever since transistor cost stopped decreasing, customized programmable platforms, such as field-programmable gate arrays (FPGAs), became a major way to improve software execution performance and energy consumption. While ...

    • Loop pipelining in high-level synthesis with CCC 

      Dimitriou G., Dossis M., Stamoulis G. (2017)
      High-level synthesis allows the use of high-level programming languages for hardware design. Traditional programming with the C and ADA languages can lead to efficient hardware description through recently developed ...

    • Minimal-area loop pipelining for high-level synthesis with CCC 

      Dimitriou G., Dossis M., Stamoulis G. (2017)
      Increased complexity of computer hardware makes close to impossible to rely on hand-coding at the-level of HDLs for digital hardware design. High-level synthesis can be employed instead, in order to automatically obtain ...

    • Operation Dependencies in Loop Pipelining for High-Level Synthesis 

      Dimitriou G., Dossis M., Stamoulis G. (2018)
      Research and industry interest in high-level synthesis has been renewed in the last few years, proven by the introduction of new tools or improved versions of existing tools. Academic tools like Gaut or CCC have recently ...

    • Resolving Loop Pipelining Issues in the CCC High-level Synthesis E-CAD Framework 

      Dossis M., Dimitriou G. (2018)
      Academic High-level Synthesis tools like CustomCoprocessorsCompiler have recently evolved in new versions with expanded functionality and more aggressive optimization schemes in order to satisfy hardware implementation ...

    • SoCLog: A real-time, automatically generated logging and profiling mechanism for FPGA-based Systems on Chip 

      Parnassos I., Skrimponis P., Zindros G., Bellas N. (2016)
      Recent advances in FPGA technology and the proliferation of High Level Synthesis (HLS) tools makes it possible to implement complex System on Chip (SoC) designs that realize complete applications in a single FPGA device. ...

    • Source-level compiler optimizations for high-level synthesis 

      Dimitriou G., Chatzianastasiou G., Tsakyridis A., Stamoulis G., Dossis M. (2016)
      With high-level synthesis becoming the preferred method for hardware design, tools that operate on high-level programming languages and optimize hardware output are crucial for successful synthesis. In high-level synthesis, ...