Auflistung Nach Schlagwort "Dynamic random access storage"
Anzeige der Dokumente 1-6 von 6
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High-speed optical cache memory as single-level shared cache in chip-multiprocessor architectures
(2015)We present an optical bus-based Chip Multiprocessor architecture where the processing cores share an optical single-level cache unit. Physically, the optical cache is implemented externally in a separate chip located next ... -
Increasing the Profit of Cloud Providers through DRAM Operation at Reduced Margins
(2020)Energy reduction is a key objective in cloud computing, and DRAM memories are responsible for an important amount of the energy consumption of data center nodes. Vendors adopt very conservative margins for DRAM operating ... -
Low power general purpose loop acceleration for NDP applications
(2020)Modern processor architectures face a throughput scaling problem as the performance bottleneck shifts from the core pipeline to the data transfer operations between the dynamic random access memory (DRAM) and the processor ... -
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis
(2022)Traditional processor architectures utilize an external DRAM for data storage, while they also operate under worst-case timing constraints. Such designs are heavily constrained by the delay costs of the data transfer between ... -
Near Data Processing Performance Improvement Prediction via Metric-Based Workload Classification
(2022)Contrary to the improvement of CPU capabilities, traditional DRAM evolution faced significant challenges that render it the main performance bottleneck in contemporary systems. Data-Intensive applications such as Machine ... -
An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memory
(2016)We present an optical bus-based chip-multiprocessor architecture where the processing cores share an optical single-level cache implemented in a separate chip next to the Central-Processing-Unit (CPU) die. The interconnection ...