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Πλοήγηση ανά Θέμα "Computer hardware"

Αποτελέσματα 1-17 από 17

    • AcHEe: Evaluating approximate computing and heterogeneity for energy efficiency 

      Koutsovasilis P., Kalogirou C., Konstantas C., Maroudas M., Spyrou M., Antonopoulos C.D. (2018)
      Energy efficiency is lately a major concern for computer engineers, at the levels of both software and hardware. A popular path is the exploitation of heterogeneity and accelerator-based systems, which combine different ...

    • COSMOS educational toolkit 

      Skrimponis P., Makris N., Rajguru S.B., Cheng K., Ostrometzky J., Ford E., Kostic Z., Zussman G., Korakis T. (2020)
      This paper focuses on the K-12 educational activities of COSMOS-<u>C</u>loud enhanced <u>O</u>pen <u>S</u>oftware defined <u>MO</u>bile wireless testbed for city-<u>S</u>cale deployment. The COSMOS wireless reasearch testbed ...

    • DReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenter 

      Bielski M., Syrigos I., Katrinis K., Syrivelis D., Reale A., Theodoropoulos D., Alachiotis N., Pnevmatikatos D., Pap E.H., Zervas G., Mishra V., Saljoghei A., Rigo A., Fernando Zazo J., Lopez-Buedo S., Torrents M., Zyulkyarov F., Enrico M., Gonzalez De DIos O. (2018)
      Current datacenters are based on server machines, whose mainboard and hardware components form the baseline, monolithic building block that the rest of the system software, middleware and application stack are built upon. ...

    • Efficient solution of large sparse linear systems in modern hardware 

      Fevgas A., Daloukas K., Tsompanopoulou P., Bozanis P. (2016)
      The solution of large-scale sparse linear systems arises in numerous scientific and engineering problems. Typical examples involve study of many real world multi-physics problems and the analysis of electric power systems. ...

    • An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits 

      Karakonstantis G., Tovletoglou K., Mukhanov L., Vandierendonck H., Nikolopoulos D.S., Lawthers P., Koutsovasilis P., Maroudas M., Antonopoulos C.D., Kalogirou C., Bellas N., Lalis S., Venugopal S., Prat-Pérez A., Lampropulos A., Kleanthous M., Diavastos A., Hadjilambrou Z., Nikolaou P., Sazeides Y., Trancoso P., Papadimitriou G., Kaliorakis M., Chatzidimitriou A., Gizopoulos D., Das S. (2018)
      The explosive growth of Internet-connected devices will soon result in a flood of generated data, which will increase the demand for network bandwidth as well as compute power to process the generated data. Consequently, ...

    • Hardware Trojan Classification at Gate-level Netlists based on Area and Power Machine Learning Analysis 

      Liakos K.G., Georgakilas G.K., Plessas F.C. (2021)
      The 21st century has been characterized by incredible technological advancements. A key factor of this revolution is the ever-growing circuits complexity that are the core components of all electronic devices. This revolution ...

    • A low-power VLSI architecture for intra and inter prediction in H.264 

      Koziri, M. G.; Stamoulis, G. I.; Katsvounidis, I. X. (2006)
      The H.264 video coding standard can achieve considerably higher coding efficiency than previous standards. The keys to this high code efficiency are mainly the two prediction modes (Intra & Inter) provided by the standard. ...

    • Massively parallel programming models used as hardware description languages: The OpenCL case 

      Owaida, M.; Bellas, N.; Antonopoulos, C. D.; Daloukas, K.; Antoniadis, C. (2011)
      The problem of automatically generating hardware modules from high level application representations has been at the forefront of EDA research during the last few years. In this paper, we introduce a methodology to ...

    • Minimal-area loop pipelining for high-level synthesis with CCC 

      Dimitriou G., Dossis M., Stamoulis G. (2017)
      Increased complexity of computer hardware makes close to impossible to rely on hand-coding at the-level of HDLs for digital hardware design. High-level synthesis can be employed instead, in order to automatically obtain ...

    • On interconnecting and orchestrating components in disaggregated data centers: The dReDBox project vision 

      Katrinis K., Zervas G., Pnevmatikatos D., Syrivelis D., Alexoudi T., Theodoropoulos D., Raho D., Pinto C., Espina F., Lopez-Buedo S., Chen Q., Nemirovsky M., Roca D., Klos H., Berends T. (2016)
      Computing systems servers-low-or high-end ones have been traditionally designed and built using a main-board and its hardware components as a 'hard' monolithic building block; this formed the base unit on which the system ...

    • OpenDwarfs: Characterization of Dwarf-Based Benchmarks on Fixed and Reconfigurable Architectures 

      Krommydas K., Feng W.-C., Antonopoulos C.D., Bellas N. (2016)
      The proliferation of heterogeneous computing platforms presents the parallel computing community with new challenges. One such challenge entails evaluating the efficacy of such parallel architectures and identifying the ...

    • Operation Dependencies in Loop Pipelining for High-Level Synthesis 

      Dimitriou G., Dossis M., Stamoulis G. (2018)
      Research and industry interest in high-level synthesis has been renewed in the last few years, proven by the introduction of new tools or improved versions of existing tools. Academic tools like Gaut or CCC have recently ...

    • Rack-scale disaggregated cloud data centers: The dReDBox project vision 

      Katrinis K., Syrivelis D., Pnevmatikatos D., Zervas G., Theodoropoulos D., Koutsopoulos I., Hasharoni K., Raho D., Pinto C., Espina F., Lopez-Buedo S., Chen Q., Nemirovsky M., Roca D., Klos H., Berends T. (2016)
      For quite some time now, computing systems servers, whether low-power or high-end ones designs are created around a common design principle: the main-board and its hardware components form a baseline, monolithic building ...

    • Resolving Loop Pipelining Issues in the CCC High-level Synthesis E-CAD Framework 

      Dossis M., Dimitriou G. (2018)
      Academic High-level Synthesis tools like CustomCoprocessorsCompiler have recently evolved in new versions with expanded functionality and more aggressive optimization schemes in order to satisfy hardware implementation ...

    • A software-defined architecture and prototype for disaggregated memory rack scale systems 

      Syrivelis D., Reale A., Katrinis K., Syrigos I., Bielski M., Theodoropoulos D., Pnevmatikatos D.N., Zervas G. (2018)
      Disaggregation and rack-scale systems have the potential of drastically increasing TCO and utilization of cloud datacenters, while maintaining performance. In this paper, we present a novel rack-scale system architecture ...

    • Source-level compiler optimizations for high-level synthesis 

      Dimitriou G., Chatzianastasiou G., Tsakyridis A., Stamoulis G., Dossis M. (2016)
      With high-level synthesis becoming the preferred method for hardware design, tools that operate on high-level programming languages and optimize hardware output are crucial for successful synthesis. In high-level synthesis, ...

    • Synthesis of platform architectures from OpenCL programs 

      Owaida, M.; Bellas, N.; Daloukas, K.; Antonopoulos, C. D. (2011)
      The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this paper, we use OpenCL, an industry supported ...