Sfoglia per Soggetto "Timing circuits"
Items 21-40 di 48
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Frequency-limited reduction of RLCK circuits via second-order balanced truncation
(2021)Second-order formulation using susceptance elements has become very effective in modeling on-chip inductive couplings. Several prior works have proposed model order reduction techniques for RLCK circuits, mostly based on ... -
Graph-Based Sparsification and Synthesis of Dense Matrices in the Reduction of RLC Circuits
(2021)The integration of more components into modern integrated circuits (ICs) has led to very large RLC parasitic networks consisting of millions of nodes that have to be simulated in many times or frequencies to verify the ... -
Graph-based STA for asynchronous controllers
(2020)We present a Graph-based Asynchronous Static Timing Analysis (ASTA) methodology for Asynchronous Control Circuits, which pessimistically computes Critical Cycle(s), instead of Critical Paths, without cycle cutting. Its ... -
Instruction-based timing analysis in pipelined processors
(2019)Traditional timing analysis techniques for microprocessor design are based on the static analysis approach, in which clock frequency is set in accord with the worst-case delay in the processor circuit operation, regardless ... -
Instruction-Flow-Based Timing Analysis in Pipelined Processors
(2019)Microprocessor design utilizes timing analysis in order to establish the maximal operation clock speed of the circuit. In static timing analysis, clock frequency is set in accord with the worst-case delay in the circuit ... -
Intrusion Detection and Botnet Prevention Circuit for IoT Devices
(2020)The need for secure and trustworthy devices has become the main question in the Internet of Things market nowadays. This work aims to introduce a circuit connected inline to the device's power supply and analyze its behavior. ... -
Large scale circuit simulation exploiting combinatorial multigrid on massively parallel architectures
(2018)The complexity of modern very large scale integrated circuits renders circuit simulation very essential in the design process, as it is the only feasible way to verify circuit's behaviour prior to manufacturing. The heart ... -
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
(2022)With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ... -
A low-complexity bit-efficient Neuromorphic Astrocyte-Neuron Circuit
(2021)Experimental and computational evidence accumulated over the last few decades suggests that astrocytes should be requisite and active constituents in neuronal information processing by providing appropriate feedback control ... -
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis
(2022)Traditional processor architectures utilize an external DRAM for data storage, while they also operate under worst-case timing constraints. Such designs are heavily constrained by the delay costs of the data transfer between ... -
Metal stack and partitioning exploration for monolithic 3D ICs
(2020)In this work, we investigate the effect of metal stack and tier 3D IC partitioning methodologies on the Quality of Results (QoR) of monolithic 3D circuits compared to their 2D counterparts. Two interconnect options are ... -
A Novel Low-power Neuromorphic Circuit based on Izhikevich Model
(2021)In recent years, scientists strove to create devices that may ameliorate patients' lives who suffer from a neuronal disease. These devices are mainly based on neuromorphic circuits and usually employ mathematical equations. ... -
On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron Technologies
(2021)Soft errors constitute a crucial reliability concern for the Integrated Circuits (ICs) as the continuous CMOS technology downscaling renders them vulnerable to radiation-induced hazards. Therefore, the Soft Error Rate (SER) ... -
On the Sparsification of the Reluctance Matrix in RLCk Circuit Transient Analysis
(2018)The ever increasing frequency scaling of contemporary very large scale integrated circuits has introduced the necessity to factor in signal integrity the analysis of inductive effects arising within the different blocks ... -
Performance evaluation of network coding and packet skipping in IEEE 802.15.4-based real-time wireless sensor networks
(2011)In a number of application domains, the volatility of the monitored environment where Wireless Sensor Networks (WSNs) operate engenders timing constraints on the generation, processing, and communication of sensory data. ... -
A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology
(2019)A considerable disadvantage that comes with the downscaling of the CMOS technology is the ever-increasing susceptibility of Integrated Circuits (ICs) to soft errors. Therefore, the study of the radiation-induced transient ... -
A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine
(2018)As technologies continue to shrink, industry seeks even faster ultra-low power ICs, requiring more accurate estimation of the worst case delay. Although traditional Static Timing Analysis (STA) methods incorporate data ... -
A printed-circuit heat exchanger consideration by exploiting an Al2O3-water nanofluid: Effect of the nanoparticles interfacial layer on heat transfer
(2021)Supercritical carbon dioxide (S-CO2) Brayton cycle is an encouraging power conversion technology pertaining to waste heat recovery applications, because of the high compactness and efficiency it presents. A key technological ... -
RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening
(2022)The manufacturing of modern Integrated Circuits (ICs), resistant against faults caused by ionising radiation, has become quite challenging due to the rapid advancement of VLSI technology. Additionally, the Radiation Hardening ... -
RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraints
(2021)The continuous evolution of VLSI technology as well as the device shrinking render the Integrated Circuits more susceptible to hazards caused by ionising radiation, as Soft Errors. Moreover, the Radiation Hardening process, ...