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dc.creatorPapalekas D., Tziouvaras A., Floros G., Dimitriou G., Dossis M., Stamoulis G.en
dc.date.accessioned2023-01-31T09:43:44Z
dc.date.available2023-01-31T09:43:44Z
dc.date.issued2022
dc.identifier10.1109/MOCAST54814.2022.9837704
dc.identifier.isbn9781665467179
dc.identifier.urihttp://hdl.handle.net/11615/77750
dc.description.abstractContrary to the improvement of CPU capabilities, traditional DRAM evolution faced significant challenges that render it the main performance bottleneck in contemporary systems. Data-Intensive applications such as Machine Learning and Graph Processing algorithms depend on time and energy consuming transactions between the memory bus and the CPU caches. The emergence of 3D-Stacked memories that provide a very high bandwidth led to the exploration of the Process-In-Memory (PIM) paradigm where logic is added to the memory die and data are being processed where they reside. To fully exploit this model, there is a need to methodically determine the portions of code that are better fitted for Near-Data-Processing (NDP). To this extend, in this work, after presenting the key trends of the research field and examine proposed criteria, we simplify the process of a priori decision of a block's suitability by proposing a two-step metric-based application categorization able to predict the applications behavior when offloaded for NDP. © 2022 IEEE.en
dc.language.isoenen
dc.source2022 11th International Conference on Modern Circuits and Systems Technologies, MOCAST 2022en
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85136115899&doi=10.1109%2fMOCAST54814.2022.9837704&partnerID=40&md5=04e2201640fe8e5e0f1539234da2eea1
dc.subjectCache memoryen
dc.subjectData handlingen
dc.subjectMachine learningen
dc.subjectThree dimensional integrated circuitsen
dc.subject3D-stacked memoryen
dc.subjectData-intensive applicationen
dc.subjectEnergyen
dc.subjectGraph processingen
dc.subjectMachine-learningen
dc.subjectNear-data-processingen
dc.subjectPerformance bottlenecksen
dc.subjectProcessing algorithmsen
dc.subjectProcessing performanceen
dc.subjectProcessing-in-memoryen
dc.subjectDynamic random access storageen
dc.subjectInstitute of Electrical and Electronics Engineers Inc.en
dc.titleNear Data Processing Performance Improvement Prediction via Metric-Based Workload Classificationen
dc.typeconferenceItemen


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