| dc.creator | Papalekas D., Tziouvaras A., Floros G., Dimitriou G., Dossis M., Stamoulis G. | en |
| dc.date.accessioned | 2023-01-31T09:43:44Z | |
| dc.date.available | 2023-01-31T09:43:44Z | |
| dc.date.issued | 2022 | |
| dc.identifier | 10.1109/MOCAST54814.2022.9837704 | |
| dc.identifier.isbn | 9781665467179 | |
| dc.identifier.uri | http://hdl.handle.net/11615/77750 | |
| dc.description.abstract | Contrary to the improvement of CPU capabilities, traditional DRAM evolution faced significant challenges that render it the main performance bottleneck in contemporary systems. Data-Intensive applications such as Machine Learning and Graph Processing algorithms depend on time and energy consuming transactions between the memory bus and the CPU caches. The emergence of 3D-Stacked memories that provide a very high bandwidth led to the exploration of the Process-In-Memory (PIM) paradigm where logic is added to the memory die and data are being processed where they reside. To fully exploit this model, there is a need to methodically determine the portions of code that are better fitted for Near-Data-Processing (NDP). To this extend, in this work, after presenting the key trends of the research field and examine proposed criteria, we simplify the process of a priori decision of a block's suitability by proposing a two-step metric-based application categorization able to predict the applications behavior when offloaded for NDP. © 2022 IEEE. | en |
| dc.language.iso | en | en |
| dc.source | 2022 11th International Conference on Modern Circuits and Systems Technologies, MOCAST 2022 | en |
| dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85136115899&doi=10.1109%2fMOCAST54814.2022.9837704&partnerID=40&md5=04e2201640fe8e5e0f1539234da2eea1 | |
| dc.subject | Cache memory | en |
| dc.subject | Data handling | en |
| dc.subject | Machine learning | en |
| dc.subject | Three dimensional integrated circuits | en |
| dc.subject | 3D-stacked memory | en |
| dc.subject | Data-intensive application | en |
| dc.subject | Energy | en |
| dc.subject | Graph processing | en |
| dc.subject | Machine-learning | en |
| dc.subject | Near-data-processing | en |
| dc.subject | Performance bottlenecks | en |
| dc.subject | Processing algorithms | en |
| dc.subject | Processing performance | en |
| dc.subject | Processing-in-memory | en |
| dc.subject | Dynamic random access storage | en |
| dc.subject | Institute of Electrical and Electronics Engineers Inc. | en |
| dc.title | Near Data Processing Performance Improvement Prediction via Metric-Based Workload Classification | en |
| dc.type | conferenceItem | en |