dc.creator | Maqsood T., Tziritas N., Loukopoulos T., Madani S.A., Khan S.U., Xu C.-Z. | en |
dc.date.accessioned | 2023-01-31T08:57:12Z | |
dc.date.available | 2023-01-31T08:57:12Z | |
dc.date.issued | 2017 | |
dc.identifier | 10.1109/TSUSC.2017.2706620 | |
dc.identifier.issn | 23773782 | |
dc.identifier.uri | http://hdl.handle.net/11615/76328 | |
dc.description.abstract | Recent advances in chip design and integration technologies have led to the development of Single-Chip Cloud computers which are a microcosm of cloud datacenters. Those computers are based on Network-on-Chip (NoC) architectures with deep memory hierarchies. Developing scheduling algorithms to reduce data access latency as well as energy consumption is a major challenge for such architectures. In this paper, we propose a set of algorithms to jointly address the problem of task scheduling and data allocation in a unified approach. Moreover, we present a feasible system model for NoC based multicores considering a three-level memory hierarchy that effectively captures the energy consumed by various elements of system including: processing cores, caches, and NoC subsystem. Simulation results show the superiority of proposed algorithms compared to two state-of-the-art algorithms found in the literature. The experimental results clearly indicate that algorithms performing data and task scheduling in a joint fashion are superior against techniques implementing task and data scheduling separately. © 2016 IEEE. | en |
dc.language.iso | en | en |
dc.source | IEEE Transactions on Sustainable Computing | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85045756977&doi=10.1109%2fTSUSC.2017.2706620&partnerID=40&md5=c6ffadd1b2ae80bab70bddb3ab5d6393 | |
dc.subject | Cache memory | en |
dc.subject | Energy utilization | en |
dc.subject | Memory architecture | en |
dc.subject | Multitasking | en |
dc.subject | Network architecture | en |
dc.subject | Network-on-chip | en |
dc.subject | Scheduling | en |
dc.subject | Scheduling algorithms | en |
dc.subject | Servers | en |
dc.subject | Data allocation | en |
dc.subject | Data scheduling | en |
dc.subject | Memory hierarchy | en |
dc.subject | Network-on-chip architectures | en |
dc.subject | NoC-based multicores | en |
dc.subject | Single-chip cloud computers | en |
dc.subject | Task-scheduling | en |
dc.subject | Unified approach | en |
dc.subject | Green computing | en |
dc.subject | Institute of Electrical and Electronics Engineers Inc. | en |
dc.title | Leveraging on deep memory hierarchies to minimize energy consumption and data access latency on single-chip cloud computers | en |
dc.type | journalArticle | en |