dc.creator | Maniotis P., Gitzenis S., Tassiulas L., Pleros N. | en |
dc.date.accessioned | 2023-01-31T08:56:49Z | |
dc.date.available | 2023-01-31T08:56:49Z | |
dc.date.issued | 2016 | |
dc.identifier | 10.1016/j.osn.2016.05.001 | |
dc.identifier.issn | 15734277 | |
dc.identifier.uri | http://hdl.handle.net/11615/76275 | |
dc.description.abstract | We present an optical bus-based chip-multiprocessor architecture where the processing cores share an optical single-level cache implemented in a separate chip next to the Central-Processing-Unit (CPU) die. The interconnection system is realized through Wavelength-Division-Multiplexed optical interfaces connecting the shared cache with the cores and the Main-Memory via spatial-multiplexed waveguides. Evaluating the proposed approach, we realize system-level simulations of a wide-range parallel workloads using Gem5. Optical cache architecture is compared against the conventional one that uses dedicated on-chip Level-1 electronic caches and a shared Level-2 cache. Results show significant Level-1 miss rate reduction of up to 96% for certain cases; on average, a performance speed-up of 19.4% or cache capacity requirements reduction of 63% is attained. Combined with high-bandwidth CPU-Dynamic Random Access Memory (DRAM) bus solutions based on optical interconnects, the proposed design is a promising architecture bridging the gap between high-speed optically connected CPU-DRAM schemes and high-speed optical memory technologies. © 2016 Elsevier B.V. | en |
dc.language.iso | en | en |
dc.source | Optical Switching and Networking | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84969915375&doi=10.1016%2fj.osn.2016.05.001&partnerID=40&md5=28af8c61180eda60a5a10bc7d8b51522 | |
dc.subject | Adaptive systems | en |
dc.subject | Buses | en |
dc.subject | Dynamic random access storage | en |
dc.subject | Image coding | en |
dc.subject | Memory architecture | en |
dc.subject | Multiplexing | en |
dc.subject | Multiprocessing systems | en |
dc.subject | Program processors | en |
dc.subject | Random access storage | en |
dc.subject | Wavelength division multiplexing | en |
dc.subject | Cache architecture | en |
dc.subject | Chip Multiprocessor | en |
dc.subject | Dynamic random access memory | en |
dc.subject | In-chip | en |
dc.subject | Interconnection systems | en |
dc.subject | Shared cache | en |
dc.subject | System level simulation | en |
dc.subject | Wavelength division multiplexed | en |
dc.subject | Cache memory | en |
dc.subject | Elsevier B.V. | en |
dc.title | An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memory | en |
dc.type | journalArticle | en |