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Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL
dc.creator | Georgakidis C., Sotiriou C. | en |
dc.date.accessioned | 2023-01-31T07:40:12Z | |
dc.date.available | 2023-01-31T07:40:12Z | |
dc.date.issued | 2020 | |
dc.identifier | 10.1109/DFT50435.2020.9250918 | |
dc.identifier.isbn | 9781728194578 | |
dc.identifier.uri | http://hdl.handle.net/11615/72042 | |
dc.description.abstract | Reduction in device feature sizes and supply voltage renders modern Integrated Circuits (ICs) more susceptible to Soft Errors (SEs), i.e. Transient Faults caused by ionising radiation. Moreover, the RADiation HARDening design flow differs from the standard design flow and currently suffers from insufficient industrial EDA tool support. R-Abax is an academic, Displacement-driven RADHARD legalisation algorithm, based on the Triple Modular Redundancy (TMR) technique, solely for Flip-Flops (FF). R-Abax ensures that a particle strike will only affect one FF of the TMR triplet, by enforcing minimum spacing constraints among FF triplets. Although the Displacement-driven R-Abax algorithm easily satisfies the spacing constraints, its Quality of Results (QoR) depends strongly on the QoR of the original placement. In this work, we propose an improved version of R-Abax, which considers the circuit Total Half-Perimeter Wire Length (HPWL) when evaluating cell moves. Experimental results indicate that the HPWL-driven R-Abax can achieve an improvement in Power, Performance and Area (PPA), compared to the Displacement-driven version. For the HPWL-driven R-Abax, as with the original version, larger minimum spacing constraints between triplet FFs does not significantly affect the QoR, rendering the proposed RADHARD flow attractive for achieving Transient Faults mitigation. © 2020 IEEE. | en |
dc.language.iso | en | en |
dc.source | 33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020 | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85097646388&doi=10.1109%2fDFT50435.2020.9250918&partnerID=40&md5=ce8e77bf6d58825f6417e655dd486018 | |
dc.subject | Authentication | en |
dc.subject | Contracts | en |
dc.subject | Defects | en |
dc.subject | Design for testability | en |
dc.subject | Fault tolerance | en |
dc.subject | Fault tolerant computer systems | en |
dc.subject | Flip flop circuits | en |
dc.subject | Hardening | en |
dc.subject | Integrated circuit design | en |
dc.subject | Ionizing radiation | en |
dc.subject | Nanotechnology | en |
dc.subject | VLSI circuits | en |
dc.subject | Design flows | en |
dc.subject | Feature sizes | en |
dc.subject | Integrated circuits (ICs) | en |
dc.subject | Quality of results | en |
dc.subject | Standard design flow | en |
dc.subject | Supply voltages | en |
dc.subject | Transient faults | en |
dc.subject | Triple modular redundancy | en |
dc.subject | Radiation hardening | en |
dc.subject | Institute of Electrical and Electronics Engineers Inc. | en |
dc.title | Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL | en |
dc.type | conferenceItem | en |
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