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dc.creatorGeorgakidis C., Sotiriou C.en
dc.date.accessioned2023-01-31T07:40:12Z
dc.date.available2023-01-31T07:40:12Z
dc.date.issued2020
dc.identifier10.1109/DFT50435.2020.9250918
dc.identifier.isbn9781728194578
dc.identifier.urihttp://hdl.handle.net/11615/72042
dc.description.abstractReduction in device feature sizes and supply voltage renders modern Integrated Circuits (ICs) more susceptible to Soft Errors (SEs), i.e. Transient Faults caused by ionising radiation. Moreover, the RADiation HARDening design flow differs from the standard design flow and currently suffers from insufficient industrial EDA tool support. R-Abax is an academic, Displacement-driven RADHARD legalisation algorithm, based on the Triple Modular Redundancy (TMR) technique, solely for Flip-Flops (FF). R-Abax ensures that a particle strike will only affect one FF of the TMR triplet, by enforcing minimum spacing constraints among FF triplets. Although the Displacement-driven R-Abax algorithm easily satisfies the spacing constraints, its Quality of Results (QoR) depends strongly on the QoR of the original placement. In this work, we propose an improved version of R-Abax, which considers the circuit Total Half-Perimeter Wire Length (HPWL) when evaluating cell moves. Experimental results indicate that the HPWL-driven R-Abax can achieve an improvement in Power, Performance and Area (PPA), compared to the Displacement-driven version. For the HPWL-driven R-Abax, as with the original version, larger minimum spacing constraints between triplet FFs does not significantly affect the QoR, rendering the proposed RADHARD flow attractive for achieving Transient Faults mitigation. © 2020 IEEE.en
dc.language.isoenen
dc.source33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020en
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85097646388&doi=10.1109%2fDFT50435.2020.9250918&partnerID=40&md5=ce8e77bf6d58825f6417e655dd486018
dc.subjectAuthenticationen
dc.subjectContractsen
dc.subjectDefectsen
dc.subjectDesign for testabilityen
dc.subjectFault toleranceen
dc.subjectFault tolerant computer systemsen
dc.subjectFlip flop circuitsen
dc.subjectHardeningen
dc.subjectIntegrated circuit designen
dc.subjectIonizing radiationen
dc.subjectNanotechnologyen
dc.subjectVLSI circuitsen
dc.subjectDesign flowsen
dc.subjectFeature sizesen
dc.subjectIntegrated circuits (ICs)en
dc.subjectQuality of resultsen
dc.subjectStandard design flowen
dc.subjectSupply voltagesen
dc.subjectTransient faultsen
dc.subjectTriple modular redundancyen
dc.subjectRadiation hardeningen
dc.subjectInstitute of Electrical and Electronics Engineers Inc.en
dc.titleRadiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWLen
dc.typeconferenceItemen


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