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RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraints
dc.creator | Georgakidis C., Lilitsis I., Stanimeropoulos G., Sotiriou C. | en |
dc.date.accessioned | 2023-01-31T07:40:11Z | |
dc.date.available | 2023-01-31T07:40:11Z | |
dc.date.issued | 2021 | |
dc.identifier | 10.1109/DFT52944.2021.9568290 | |
dc.identifier.isbn | 9781665416092 | |
dc.identifier.issn | 25761501 | |
dc.identifier.uri | http://hdl.handle.net/11615/72037 | |
dc.description.abstract | The continuous evolution of VLSI technology as well as the device shrinking render the Integrated Circuits more susceptible to hazards caused by ionising radiation, as Soft Errors. Moreover, the Radiation Hardening process, i.e. rendering electronic cells and circuits resistant to damage or malfunction caused by ionising radiation, differs from the standard design flow and suffers currently from insufficient support from industrial EDA tools. R-Abax is an academic tool able to satisfy user-specified spacing constraints between Triple Modular Redundancy (TMR) members, during the Place&Route process, specifically during the Legalisation step. The spacing constraints enforced by R-Abax ensure that a particle strike will only affect at most one TMR triplet member. R-Abax may operate in Displacement-driven and HPWL-driven mode. In this work, we propose an evolution of R-Abax, RADPlace, a Timing-Aware Detailed Placement algorithm, aiming to improve the circuit timing, while enforcing the user-specified TMR groups spacing constraints. Experimental results indicate that RADPlace Detailed Placement achieves, an average 18% improvement to circuit performance, with negligible changes to area and power consumption. © 2021 IEEE | en |
dc.language.iso | en | en |
dc.source | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85136358107&doi=10.1109%2fDFT52944.2021.9568290&partnerID=40&md5=a41111655c897570c2dbca1c40c23613 | |
dc.subject | Hardening | en |
dc.subject | Ionizing radiation | en |
dc.subject | Timing circuits | en |
dc.subject | Detailed placement | en |
dc.subject | Electronic cells | en |
dc.subject | Electronics circuits | en |
dc.subject | Hardening process | en |
dc.subject | Placement scheme | en |
dc.subject | Soft error | en |
dc.subject | Spacing constraint | en |
dc.subject | Timing-driven | en |
dc.subject | Triple modular redundancy | en |
dc.subject | VLSI technology | en |
dc.subject | Radiation hardening | en |
dc.subject | Institute of Electrical and Electronics Engineers Inc. | en |
dc.title | RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraints | en |
dc.type | conferenceItem | en |
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