Show simple item record

dc.creatorGeorgakidis C., Lilitsis I., Stanimeropoulos G., Sotiriou C.en
dc.date.accessioned2023-01-31T07:40:11Z
dc.date.available2023-01-31T07:40:11Z
dc.date.issued2021
dc.identifier10.1109/DFT52944.2021.9568290
dc.identifier.isbn9781665416092
dc.identifier.issn25761501
dc.identifier.urihttp://hdl.handle.net/11615/72037
dc.description.abstractThe continuous evolution of VLSI technology as well as the device shrinking render the Integrated Circuits more susceptible to hazards caused by ionising radiation, as Soft Errors. Moreover, the Radiation Hardening process, i.e. rendering electronic cells and circuits resistant to damage or malfunction caused by ionising radiation, differs from the standard design flow and suffers currently from insufficient support from industrial EDA tools. R-Abax is an academic tool able to satisfy user-specified spacing constraints between Triple Modular Redundancy (TMR) members, during the Place&Route process, specifically during the Legalisation step. The spacing constraints enforced by R-Abax ensure that a particle strike will only affect at most one TMR triplet member. R-Abax may operate in Displacement-driven and HPWL-driven mode. In this work, we propose an evolution of R-Abax, RADPlace, a Timing-Aware Detailed Placement algorithm, aiming to improve the circuit timing, while enforcing the user-specified TMR groups spacing constraints. Experimental results indicate that RADPlace Detailed Placement achieves, an average 18% improvement to circuit performance, with negligible changes to area and power consumption. © 2021 IEEEen
dc.language.isoenen
dc.sourceProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTen
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85136358107&doi=10.1109%2fDFT52944.2021.9568290&partnerID=40&md5=a41111655c897570c2dbca1c40c23613
dc.subjectHardeningen
dc.subjectIonizing radiationen
dc.subjectTiming circuitsen
dc.subjectDetailed placementen
dc.subjectElectronic cellsen
dc.subjectElectronics circuitsen
dc.subjectHardening processen
dc.subjectPlacement schemeen
dc.subjectSoft erroren
dc.subjectSpacing constrainten
dc.subjectTiming-drivenen
dc.subjectTriple modular redundancyen
dc.subjectVLSI technologyen
dc.subjectRadiation hardeningen
dc.subjectInstitute of Electrical and Electronics Engineers Inc.en
dc.titleRADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraintsen
dc.typeconferenceItemen


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record