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MNCM: A Critical Node Matching Approach to Scheduling for Input Buffered Switches With No Speedup
dc.creator | Tabatabaee, V. | en |
dc.creator | Tassiulas, L. | en |
dc.date.accessioned | 2015-11-23T10:49:18Z | |
dc.date.available | 2015-11-23T10:49:18Z | |
dc.date.issued | 2009 | |
dc.identifier | 10.1109/tnet.2008.925091 | |
dc.identifier.issn | 1063-6692 | |
dc.identifier.uri | http://hdl.handle.net/11615/33519 | |
dc.description.abstract | In this paper, we use fluid model techniques to establish new results for the throughput of input-buffered switches. Dai and Prabhakar have shown that any maximal size matching algorithm with speedup of 2 achieves 100% throughput. We introduce the maximum node containing matching (MNCM), which is a new class of matching algorithms that achieve 100% throughput with no speedup. The only assumption on the arrival processes is they satisfy the strong law of large numbers (SLLN). The MNCM policies only need to include ports whose weight (backlog) are above a threshold in the matching rather than finding a matching with maximum total weight. This simplified requirement enables us to introduce a new matching algorithm, maximum first matching (MFM), with O(N(2.5)) complexity. We show that MFM is a low-complexity algorithm with good delay performance. We also provide a deterministic upper bound for the buffering requirement of a switch with an MNCM scheduler, when the ports incoming traffic are admissible and (sigma, rho) regulated. | en |
dc.source | Ieee-Acm Transactions on Networking | en |
dc.source.uri | <Go to ISI>://WOS:000263604500023 | |
dc.subject | Input-queued switch fabrics | en |
dc.subject | scheduling | en |
dc.subject | stability analysis | en |
dc.subject | POLICIES | en |
dc.subject | Computer Science, Hardware & Architecture | en |
dc.subject | Computer Science, Theory & | en |
dc.subject | Methods | en |
dc.subject | Engineering, Electrical & Electronic | en |
dc.subject | Telecommunications | en |
dc.title | MNCM: A Critical Node Matching Approach to Scheduling for Input Buffered Switches With No Speedup | en |
dc.type | journalArticle | en |
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