dc.creator | Owaida, M. | en |
dc.creator | Bellas, N. | en |
dc.creator | Antonopoulos, C. D. | en |
dc.creator | Daloukas, K. | en |
dc.creator | Antoniadis, C. | en |
dc.creator | Krommydas, K. | en |
dc.creator | Tsoumblekas, G. | en |
dc.date.accessioned | 2015-11-23T10:41:57Z | |
dc.date.available | 2015-11-23T10:41:57Z | |
dc.date.issued | 2011 | |
dc.identifier | 10.1109/FCCM.2011.32 | |
dc.identifier.isbn | 9780769543017 | |
dc.identifier.uri | http://hdl.handle.net/11615/31513 | |
dc.description.abstract | Next generation video standards have strict and increasing performance demands due to real-time requirements and the trend towards higher frame resolutions and bit rates. Leveraging the advantages of reconfigurable logic and emerging multi-core processor architectures to exploit all levels of parallelism of such workloads is necessary to achieve real time functionality at a reasonable cost. © 2011 IEEE. | en |
dc.source.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-79958712110&partnerID=40&md5=8280f929386bff01b2d1bb77dfcc9ce1 | |
dc.subject | AVS Motion Compensation | en |
dc.subject | FPGA | en |
dc.subject | GPU | en |
dc.subject | Multi-cores | en |
dc.subject | Reconfigurable Computing | en |
dc.subject | Video Compression | en |
dc.subject | Bit rates | en |
dc.subject | Multi-core processor | en |
dc.subject | Performance comparison | en |
dc.subject | Real time | en |
dc.subject | Real time requirement | en |
dc.subject | Reconfigurable logic | en |
dc.subject | Video decoders | en |
dc.subject | Video standard | en |
dc.subject | Computer architecture | en |
dc.subject | Computers | en |
dc.subject | Field programmable gate arrays (FPGA) | en |
dc.subject | Image compression | en |
dc.subject | Reconfigurable hardware | en |
dc.subject | Motion compensation | en |
dc.title | Implementation and performance comparison of the motion compensation kernel of the AVS video decoder on FPGA, GPU and multicore processors | en |
dc.type | conferenceItem | en |