Massively parallel programming models used as hardware description languages: The OpenCL case
dc.creator | Owaida, M. | en |
dc.creator | Bellas, N. | en |
dc.creator | Antonopoulos, C. D. | en |
dc.creator | Daloukas, K. | en |
dc.creator | Antoniadis, C. | en |
dc.date.accessioned | 2015-11-23T10:41:56Z | |
dc.date.available | 2015-11-23T10:41:56Z | |
dc.date.issued | 2011 | |
dc.identifier | 10.1109/ICCAD.2011.6105349 | |
dc.identifier.isbn | 9781457713989 | |
dc.identifier.issn | 10923152 | |
dc.identifier.uri | http://hdl.handle.net/11615/31512 | |
dc.description.abstract | The problem of automatically generating hardware modules from high level application representations has been at the forefront of EDA research during the last few years. In this paper, we introduce a methodology to automatically synthesize hardware accelerators from OpenCL applications. OpenCL is a recent industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs. Our methodology maps OpenCL kernels into hardware accelerators, based on architectural templates that explicitly decouple computation from memory communication whenever this is possible. The templates can be tuned to provide a wide repertoire of accelerators that meet user performance requirements and FPGA device characteristics. Furthermore, a set of high- and low-level compiler optimizations is applied to generate optimized accelerators. Our experimental evaluation shows that the generated accelerators are tuned efficiently to match the applications memory access pattern and computational complexity, and to achieve user performance requirements. An important objective of our tool is to expand the FPGA development user base to software engineers, thereby expanding the scope of FPGAs beyond the realm of hardware design. © 2011 IEEE. | en |
dc.source.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-84855815862&partnerID=40&md5=d257fafcb2e2bccbbedbd31f6b7b3c47 | |
dc.subject | Electronic Design Automation | en |
dc.subject | Embedded Systems | en |
dc.subject | FPGA | en |
dc.subject | OpenCL | en |
dc.subject | Reconfigurable Computing | en |
dc.subject | Compiler optimizations | en |
dc.subject | Decouple computation | en |
dc.subject | Experimental evaluation | en |
dc.subject | FPGA devices | en |
dc.subject | Hardware accelerators | en |
dc.subject | Hardware design | en |
dc.subject | Hardware modules | en |
dc.subject | High level applications | en |
dc.subject | Memory access patterns | en |
dc.subject | Multi-core platforms | en |
dc.subject | Parallel programming model | en |
dc.subject | Software engineers | en |
dc.subject | User performance | en |
dc.subject | Acceleration | en |
dc.subject | Computational complexity | en |
dc.subject | Computer aided design | en |
dc.subject | Computer hardware description languages | en |
dc.subject | Field programmable gate arrays (FPGA) | en |
dc.subject | Hardware | en |
dc.subject | High level languages | en |
dc.subject | Multicore programming | en |
dc.subject | Optimization | en |
dc.subject | Parallel programming | en |
dc.subject | Program compilers | en |
dc.subject | Reconfigurable hardware | en |
dc.subject | Computer hardware | en |
dc.title | Massively parallel programming models used as hardware description languages: The OpenCL case | en |
dc.type | conferenceItem | en |
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