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dc.creatorDimitriou, G.en
dc.creatorPolychronopoulos, C.en
dc.date.accessioned2015-11-23T10:25:36Z
dc.date.available2015-11-23T10:25:36Z
dc.date.issued2005
dc.identifier.isbn3-540-29673-5
dc.identifier.issn0302-9743
dc.identifier.urihttp://hdl.handle.net/11615/27074
dc.description.abstractLoop scheduling has significant differences in multithreaded from other parallel processors. The sharing of hardware resources imposes new scheduling limitations, but it also allows a faster communication across threads. We present a multithreaded processor model, Coral 2000, with hardware extensions that support Macro Software Pipelining, a loop scheduling technique for multithreaded processors. We tested and evaluated Coral 2000 on a cycle-level simulator, using synthetic and integer SPEC benchmarks. We obtained speedups of up to 30% with respect to highly optimized superblock-based schedules on loops that exhibit limited parallelism.en
dc.source.uri<Go to ISI>://WOS:000233675500059
dc.subjectCOMPILATIONen
dc.subjectComputer Science, Artificial Intelligenceen
dc.subjectComputer Science, Informationen
dc.subjectSystemsen
dc.subjectComputer Science, Theory & Methodsen
dc.subjectTelecommunicationsen
dc.titleHardware support for multithreaded execution of loops with limited parallelismen
dc.typebookChapteren


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