Πλοήγηση ανά Θέμα "Memory architecture"
Αποτελέσματα 1-10 από 10
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Heterogeneous spectrum bands aggregation prototype with cognitive radio capabilities
(2015)This paper presents the design and simulation of an RF prototype that can provide dynamic carrier aggregation (CA) in future cognitive heterogeneous cellular networks including also access to heterogeneous technologies. ... -
Leveraging on deep memory hierarchies to minimize energy consumption and data access latency on single-chip cloud computers
(2017)Recent advances in chip design and integration technologies have led to the development of Single-Chip Cloud computers which are a microcosm of cloud datacenters. Those computers are based on Network-on-Chip (NoC) architectures ... -
Modeling, gait sequence design, and control architecture of BADGER underground robot
(2021)This letter presents the dynamic modeling, the gait sequence design, and the control architecture of the BADGER autonomous underground robot. BADGER is a modular and articulated robotic mechanism which employs inchworm ... -
Multithreading on reconfigurable hardware: A performance evaluation approach of a multicore FPGA architecture
(2021)This paper addresses the performance issues of multiple threads running on a multithreaded field programmable gate array (FPGA) multicore architecture, supported by a realtime variant of Linux operating system. The objective ... -
On the Implementation of a Software-Defined Memory Control Plane for Disaggregated Datacenters
(2022)By adopting a disaggregated hardware architecture, datacenters can achieve considerable efficiency gains and transition to a more sustainable and green future. By decoupling resources from a single monolithic server and ... -
On the statistical memory architecture exploration and optimization
(2015)The worsening of process variations and the consequent increased spreads in circuit performance and consumed power hinder the satisfaction of the targeted budgets and lead to yield loss. Corner based design and adoption ... -
An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memory
(2016)We present an optical bus-based chip-multiprocessor architecture where the processing cores share an optical single-level cache implemented in a separate chip next to the Central-Processing-Unit (CPU) die. The interconnection ... -
Parallel Fast Transform-Based Preconditioners for Large-Scale Power Grid Analysis on Graphics Processing Units (GPUs)
(2016)Efficient analysis of on-chip power delivery networks is one of the most challenging problems facing the electronic design automation industry today. The fast dc and transient simulation of power grids is necessary to ... -
Rack-scale disaggregated cloud data centers: The dReDBox project vision
(2016)For quite some time now, computing systems servers, whether low-power or high-end ones designs are created around a common design principle: the main-board and its hardware components form a baseline, monolithic building ... -
A software-defined architecture and prototype for disaggregated memory rack scale systems
(2018)Disaggregation and rack-scale systems have the potential of drastically increasing TCO and utilization of cloud datacenters, while maintaining performance. In this paper, we present a novel rack-scale system architecture ...