Auflistung Nach Schlagwort "Integrated circuit interconnects"
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Accelerating Electromigration Stress Analysis Using Low-Rank Balanced Truncation
(2022)Electromigration (EM) has become one of the most significant challenges considering longterm reliability in integrated circuit design. The problem is caused by the large current density in circuit interconnections. However, ... -
Gate Delay Estimation with Library Compatible Current Source Models and Effective Capacitance
(2021)As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate ... -
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
(2022)With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ... -
Metal stack and partitioning exploration for monolithic 3D ICs
(2020)In this work, we investigate the effect of metal stack and tier 3D IC partitioning methodologies on the Quality of Results (QoR) of monolithic 3D circuits compared to their 2D counterparts. Two interconnect options are ... -
A novel semi-analytical approach for fast electromigration stress analysis in multi-segment interconnects
(2022)As integrated circuit technologies move below 10 nm, Electromigration (EM) has become an issue of great concern for the longterm reliability due to the stricter performance, thermal and power requirements. The problem of ... -
On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron Technologies
(2021)Soft errors constitute a crucial reliability concern for the Integrated Circuits (ICs) as the continuous CMOS technology downscaling renders them vulnerable to radiation-induced hazards. Therefore, the Soft Error Rate (SER) ... -
A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects
(2019)Signoff timing analysis is essential in order to verify the proper operation of VLSI circuits. As process technologies scale down towards nanometer regimes, the fast and accurate timing analysis of interconnects has become ...