Parcourir par sujet "Dynamic random access memory"
Voici les éléments 1-2 de 2
-
Low power general purpose loop acceleration for NDP applications
(2020)Modern processor architectures face a throughput scaling problem as the performance bottleneck shifts from the core pipeline to the data transfer operations between the dynamic random access memory (DRAM) and the processor ... -
An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memory
(2016)We present an optical bus-based chip-multiprocessor architecture where the processing cores share an optical single-level cache implemented in a separate chip next to the Central-Processing-Unit (CPU) die. The interconnection ...