Parcourir par sujet "Cache memory"
Voici les éléments 1-7 de 7
-
Caching and operator cooperation policies for layered video content delivery
(2016)Distributed caching architectures have been proposed for bringing content close to requesters and the key problem is to design caching algorithms for reducing content delivery delay. The problem obtains an interesting new ... -
Distributed caching algorithms in the realm of layered video streaming
(2019)Distributed caching architectures have been proposed for bringing content close to requesters, and the key problem is to design caching algorithms for reducing content delivery delay, which determines to an extent the user ... -
High-speed optical cache memory as single-level shared cache in chip-multiprocessor architectures
(2015)We present an optical bus-based Chip Multiprocessor architecture where the processing cores share an optical single-level cache unit. Physically, the optical cache is implemented externally in a separate chip located next ... -
Leveraging on deep memory hierarchies to minimize energy consumption and data access latency on single-chip cloud computers
(2017)Recent advances in chip design and integration technologies have led to the development of Single-Chip Cloud computers which are a microcosm of cloud datacenters. Those computers are based on Network-on-Chip (NoC) architectures ... -
Near Data Processing Performance Improvement Prediction via Metric-Based Workload Classification
(2022)Contrary to the improvement of CPU capabilities, traditional DRAM evolution faced significant challenges that render it the main performance bottleneck in contemporary systems. Data-Intensive applications such as Machine ... -
A novel chip-multiprocessor architecture with optically interconnected shared L1 optical cache memory
(2014)We demonstrate a system-level CMP architecture where optical cache memories are shared among multiple processing cores through optical buses. System-level simulations show 25-45% execution time improvement and significant ... -
An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memory
(2016)We present an optical bus-based chip-multiprocessor architecture where the processing cores share an optical single-level cache implemented in a separate chip next to the Central-Processing-Unit (CPU) die. The interconnection ...