Browsing by Subject "Asynchronous circuits"
Now showing items 1-6 of 6
-
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits
(2021)In this article, unlike almost all state-of-The-Art obfuscation solutions that focus on functional/logic obfuscation, we introduce a new paradigm, called data flow obfuscation, which exploits the essence of asynchronicity. ... -
Graph-based STA for asynchronous controllers
(2020)We present a Graph-based Asynchronous Static Timing Analysis (ASTA) methodology for Asynchronous Control Circuits, which pessimistically computes Critical Cycle(s), instead of Critical Paths, without cycle cutting. Its ... -
Low power monolithic 3D IC design of asynchronous AES core
(2015)In this paper, we demonstrate, for the first time, that a monolithic 3D implementation of an asynchronous AES encryption core can achieve up to 50.3% footprint reduction, 25.7% improvement in power, 34.3% shorter wirelength ... -
Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops
(2022)We demonstrate an iterative simulation-based maximum coverage detection and elimination analysis of logic-hazards for combinational logic loops. Although the focus is on asynchronous circuits with such feedbacks, it is ... -
Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits
(2021)In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because ... -
Timing errors in sta-based gate-level simulation
(2020)In this paper, we demonstrate that conventional STA-based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local ...