• Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits 

      Simoglou S., Sotiriou C., Blias N. (2021)
      In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because ...
    • Timing errors in sta-based gate-level simulation 

      Simoglou S., Sotiriou C., Blias N. (2020)
      In this paper, we demonstrate that conventional STA-based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local ...