Πλοήγηση ανά Θέμα "Timing circuits"

A rigorous approach for the sparsification of dense matrices in model order reduction of RLC circuits

Antoniadis C., Evmorfopoulos N., Stamoulis G. (2019)

The integration of more components into modern Systems-on-Chip (SoCs) has led to very large RLC parasitic networks consisting of million of nodes, which have to be simulated in many times or frequencies to verify the proper ...

Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops

Chatzivangelis N., Valiantzas D., Sotiriou C., Lilitsis I. (2022)

We demonstrate an iterative simulation-based maximum coverage detection and elimination analysis of logic-hazards for combinational logic loops. Although the focus is on asynchronous circuits with such feedbacks, it is ...

A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects

Garyfallou D., Antoniadis C., Evmorfopoulos N., Stamoulis G. (2019)

Signoff timing analysis is essential in order to verify the proper operation of VLSI circuits. As process technologies scale down towards nanometer regimes, the fast and accurate timing analysis of interconnects has become ...

STA for mixed cyclic, acyclic circuits

Simoglou S., Sotiriou C., Valiantzas D., Sketopoulos N. (2020)

In this work, we present a Static Timing Analysis (STA) methodology for cyclic circuits with attached acyclic datapaths, as an alternative to SPICE level electrical simulation, based on ASTA (Asynchronous STA). Our methodology ...

Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits

Simoglou S., Sotiriou C., Blias N. (2021)

In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because ...

Statistical Estimation of Leakage Power Bounds in CMOS VLSI Circuits

Bountas D., Evmorfopoulos N., Dimitriou G., Dadaliaris A., Floros G., Stamoulis G. (2021)

A statistical approach for the estimation of maximum and minimum leakage power in CMOS Very Large Scale Integration (VLSI) circuits is proposed in this paper. The approach is based on the discipline of statistics known as ...

Timing errors in sta-based gate-level simulation

Simoglou S., Sotiriou C., Blias N. (2020)

In this paper, we demonstrate that conventional STA-based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local ...

TKtimer: Fast & accurate clock network pessimism removal

Kalonakis, C.; Antoniadis, C.; Giannakou, P.; Dioudis, D.; Pinitas, G.; Stamoulis, G. (2015)

As integrated circuit process technology progresses into the deep sub-micron region, the phenomenon of process variation has a growing impact on the design and analysis of digital circuits and more specifically in the ...