Sfoglia per Soggetto "Transistor level"
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Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits
(2021)In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because ... -
Timing errors in sta-based gate-level simulation
(2020)In this paper, we demonstrate that conventional STA-based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local ...