Sfoglia per Soggetto "Hardware accelerators"
Items 1-6 di 6
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Design Space Exploration of a Sparse MobileNetV2 Using High-Level Synthesis and Sparse Matrix Techniques on FPGAs
(2022)Convolution Neural Networks (CNNs) are gaining ground in deep learning and Artificial Intelligence (AI) domains, and they can benefit from rapid prototyping in order to produce efficient and low-power hardware designs. The ... -
Exploration Study on Configurable Instruction Set for Bioinformatics' Applications
(2019)In the past decade, the needs for faster data analysis with high throughput has increased dramatically. Especially in the domain of Bioinformatics and biological data analysis. A common way to overcome this issue is to ... -
Fisheye lens distortion correction on multicore and hardware accelerator platforms
(2010)Wide-angle (fisheye) lenses are often used in virtual reality and computer vision applications to widen the field of view of conventional cameras. Those lenses, however, distort images. For most real-world applications the ... -
Massively parallel programming models used as hardware description languages: The OpenCL case
(2011)The problem of automatically generating hardware modules from high level application representations has been at the forefront of EDA research during the last few years. In this paper, we introduce a methodology to ... -
On emulating hardware/software co-designed control algorithms for packet switches
(2014)Hardware accelerators in networking systems for control algorithms offer a promising approach to scale performance. To that end, several research efforts have been devoted to verify a hardware version of complex control ... -
Proteus: An architectural synthesis tool based on the stream programming paradigm
(2009)The problem of automatically generating hardware modules from a high level representation of an application has been at the forefront of EDA research in the last few years. Such an EDA methodology would potentially enable ...