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    • Gate Delay Estimation with Library Compatible Current Source Models and Effective Capacitance 

      Garyfallou D., Simoglou S., Sketopoulos N., Antoniadis C., Sotiriou C.P., Evmorfopoulos N., Stamoulis G. (2021)
      As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate ...

    • Wafer Map Defect Pattern Recognition using Imbalanced Datasets 

      Tziolas T., Theodosiou T., Papageorgiou K., Rapti A., Dimitriou N., Tzovaras D., Papageorgiou E. (2022)
      The accurate and automatic inspection of wafer maps is vital for semiconductor engineers to identify defect causes and to optimize the wafer fabrication process. This research work seeks to address the pattern recognition ...