Parcourir par sujet "SPICE"
Voici les éléments 1-11 de 11
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A completely scalable lumped-circuit model for horizontal and vertical HALL devices
(2007)A completely scalable lumped-circuit model for horizontal and vertical HALL devices is presented therein that can be efficiently implemented in SPICE-like EDA simulators. The model has been employed for the quantitative ... -
EVT-based worst case delay estimation under process variation
(2018)Manufacturing process variation in sub-20nm processes has introduced ever increasing overhead in Static Timing Analysis (STA) in order to guarantee the reliable operation of the circuit. Chip designers apply corner-based ... -
Graph-based STA for asynchronous controllers
(2020)We present a Graph-based Asynchronous Static Timing Analysis (ASTA) methodology for Asynchronous Control Circuits, which pessimistically computes Critical Cycle(s), instead of Critical Paths, without cycle cutting. Its ... -
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
(2022)With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ... -
A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions
(2008)Accurate simulation of digital circuits is an essential part of the design process. High precision models are generally used to confirm logic behavior and estimate power dissipation, which has become an extremely important ... -
A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology
(2019)A considerable disadvantage that comes with the downscaling of the CMOS technology is the ever-increasing susceptibility of Integrated Circuits (ICs) to soft errors. Therefore, the study of the radiation-induced transient ... -
Single Event Transients Generation and Propagation Flow using Commercial EDA Tools
(2021)The ever increasing demand for reliable microelectronic systems in the presence of radiation, combined with the continuous shrinking of CMOS technologies, has rendered the impact of radiation-induced voltage glitches, known ... -
A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects
(2019)Signoff timing analysis is essential in order to verify the proper operation of VLSI circuits. As process technologies scale down towards nanometer regimes, the fast and accurate timing analysis of interconnects has become ... -
STA for mixed cyclic, acyclic circuits
(2020)In this work, we present a Static Timing Analysis (STA) methodology for cyclic circuits with attached acyclic datapaths, as an alternative to SPICE level electrical simulation, based on ASTA (Asynchronous STA). Our methodology ... -
Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits
(2021)In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because ... -
Timing errors in sta-based gate-level simulation
(2020)In this paper, we demonstrate that conventional STA-based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local ...