Parcourir par sujet "Current source models"
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Gate Delay Estimation with Library Compatible Current Source Models and Effective Capacitance
(2021)As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate ... -
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
(2022)With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ...