Parcourir par sujet "Capacitance"
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Gate Delay Estimation with Library Compatible Current Source Models and Effective Capacitance
(2021)As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate ... -
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
(2022)With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ... -
A low-power CMOS VLSI circuit for signal conditioning in integrated capacitive sensors
(2004)Capacitive sensor manufacturing processes are rarely compatible with CMOS technologies and, thus, monolithic integration of sensing device and signal-conditioning IC is often not possible. Multi-chip packaging and wire ... -
Robust discretization algorithms for the numerical intergration of nonlinear PDEs with application to a generalized capacitor
(1998)Numerical integration of nonlinear (NL) partial differential equations (PDEs) is studied via approximating the original continuous-domain physical system by a discrete multidimensional (MD) and passive system, using ... -
Synthesis and characterization of activated 3D graphene via catalytic growth and chemical activation for electrochemical energy storage in supercapacitors
(2019)Activated three-dimensional graphene (3D-AGE) powders with high specific surface area have been successfully prepared by combined strategies of catalytic growth and chemical activation for application in supercapacitors. ...