• SER analysis of multiple transient faults in combinational logic 

      Paliaroutis G.I., Tsoumanis P., Dimitriou G., Stamoulis G.I. (2016)
      In the VLSI field, reliability of chips is a major issue and it becomes more significant considering the continuous technology down-scaling. Modern chips are extremely sensitive to various factors such as radiation and, ...
    • STA for mixed cyclic, acyclic circuits 

      Simoglou S., Sotiriou C., Valiantzas D., Sketopoulos N. (2020)
      In this work, we present a Static Timing Analysis (STA) methodology for cyclic circuits with attached acyclic datapaths, as an alternative to SPICE level electrical simulation, based on ASTA (Asynchronous STA). Our methodology ...