Mostrando ítems 1-7 de 7
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Efficient large-scale distance-based join queries in spatialhadoop
(2018)Efficient processing of Distance-Based Join Queries (DBJQs) in spatial databases is of paramount importance in many application domains. The most representative and known DBJQs are the K Closest Pairs Query (KCPQ) and the ... -
Energy and communication aware task mapping for MPSoCs
(2018)Minimizing energy consumption and network load is a major challenge for network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs). Efficient task and core mapping can greatly reduce the overall energy consumption ... -
Fast dynamic binary rewriting for flexible thread migration on shared-ISA heterogeneous MPSoCs
(2014)Heterogeneous MPSoCs where different types of cores share a baseline ISA but implement different operational accelerators combine programmability with flexible customization. They hold promise for high performance under ... -
High-speed optical cache memory as single-level shared cache in chip-multiprocessor architectures
(2015)We present an optical bus-based Chip Multiprocessor architecture where the processing cores share an optical single-level cache unit. Physically, the optical cache is implemented externally in a separate chip located next ... -
Implementation and performance analysis of SEAL encryption on FPGA, GPU and multi-core processors
(2011)Accelerators, such as field programmable gate arrays (FPGAs) and graphics processing units (GPUs), are special purpose processors designed to speed up compute-intensive sections of applications. FPGAs are highly customizable, ... -
Mapping and optimization of the AVS video decoder on a high performance chip multiprocessor
(2010)Modern multimedia workloads provide increased levels of quality and compression efficiency at the expense of substantially increased computational complexity. It is important to leverage the off-the-shelf emerging multi-core ... -
An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memory
(2016)We present an optical bus-based chip-multiprocessor architecture where the processing cores share an optical single-level cache implemented in a separate chip next to the Central-Processing-Unit (CPU) die. The interconnection ...