Auflistung nach Autor "Garyfallou D., Vagenas A., Antoniadis C., Massoud Y., Stamoulis G."
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Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
Garyfallou D., Vagenas A., Antoniadis C., Massoud Y., Stamoulis G. (2022)With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ...