dc.creator | Kalaitzidis K., Dimitriou G., Stamoulis G., Dossis M. | en |
dc.date.accessioned | 2023-01-31T08:29:17Z | |
dc.date.available | 2023-01-31T08:29:17Z | |
dc.date.issued | 2015 | |
dc.identifier | 10.1145/2801948.2801958 | |
dc.identifier.isbn | 9781450335515 | |
dc.identifier.uri | http://hdl.handle.net/11615/74156 | |
dc.description.abstract | Loop acceleration is a means to enhance performance of a singleor multiple-issue microprocessor core. A new edge-like processor architecture incorporates a loop accelerator directly in the out-oforder back end of the processor, forming an extended hypercube interconnected network of functional unit nodes. In this work, we have simulated a full processor pipeline of our architecture in a high-level language. In particular, we have extended the Simplescalar, a well-known processor simulator, to include our multifunctional-unit back-end design, and to support our special instructions for loop acceleration. Thus, instructions forming qualified loops are scheduled and dispatched only once for execution, remaining in the back end for all loop iterations, interchanging values in a data-flow fashion. We have also utilized the Wattch power estimation tool, which has been traditionally coupling Simplescalar to produce an estimation of power consumption during simulation, to show that our design results in significant power savings. Since loop instructions reside in the functional unit nodes during loop execution, all front end of the pipeline is turned off and the register file and the instruction cache are kept at low power at that time. Experiments conducted include simulating execution of small loop-based benchmarks from the Livermore loops, as well as longer real-life code taken from open-source mpeg video compression codes. All experiments exhibit the expected performance and power consumption improvements, verifying earlier performance measurements on the HDL model of the back end. © 2015 ACM. | en |
dc.language.iso | en | en |
dc.source | ACM International Conference Proceeding Series | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84962614405&doi=10.1145%2f2801948.2801958&partnerID=40&md5=a5b7ac1d4004cb0fd5a3e67b0f290361 | |
dc.subject | Closed loop control systems | en |
dc.subject | Computer architecture | en |
dc.subject | Computer peripheral equipment | en |
dc.subject | Computer programming languages | en |
dc.subject | Electric power utilization | en |
dc.subject | High level languages | en |
dc.subject | Information science | en |
dc.subject | Integrated circuit design | en |
dc.subject | Motion Picture Experts Group standards | en |
dc.subject | Network architecture | en |
dc.subject | Open systems | en |
dc.subject | Pipelines | en |
dc.subject | Architecture simulation | en |
dc.subject | Interconnected network | en |
dc.subject | Loop acceleration | en |
dc.subject | MPEG video compression | en |
dc.subject | Multifunctional unit | en |
dc.subject | Performance measurements | en |
dc.subject | Power estimations | en |
dc.subject | Processor architectures | en |
dc.subject | Pipeline processing systems | en |
dc.subject | Association for Computing Machinery | en |
dc.title | Performance and power simulation of a functional-unit-network processor with Simplescalar and Wattch | en |
dc.type | conferenceItem | en |