Supporting multitasking of pipelined computations on embedded parallel processor arrays
dc.creator | Syrivelis, D. | en |
dc.creator | Lalis, S. | en |
dc.date.accessioned | 2015-11-23T10:49:12Z | |
dc.date.available | 2015-11-23T10:49:12Z | |
dc.date.issued | 2009 | |
dc.identifier | 10.1109/ICPPW.2009.25 | |
dc.identifier.isbn | 9780769538037 | |
dc.identifier.issn | 15302016 | |
dc.identifier.uri | http://hdl.handle.net/11615/33502 | |
dc.description.abstract | This paper presents software support that enables seamless task restructuring and load balancing of pipelined applications at runtime, making it possible to dynamically pick the stages that will be executed as separate tasks on distinct CPUs, depending on the currently available resources and the execution context. This functionality is integrated in a development and execution framework for pipelined applications targeted at reconfigurable (in terms of interconnections), heterogeneous (in terms of architecture and/or clock speed), distributed memory, embedded Parallel Processor Arrays (PPAs). The primary motivation for this work is to support the use of PPA on-chip architectures, which are currently considered as dedicated accelerators, in a multitasking execution context where the available processor cores are distributed among concurrently executing applications. As a proof-of-concept, we discuss the execution of two pipelined applications on an FPGA-based prototype platform that features Xilinx Microblaze soft processor arrays. © 2009 IEEE. | en |
dc.source.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-77949501226&partnerID=40&md5=fb2e6ed25400a6a2e42d4d936388cfcb | |
dc.subject | Dynamic load balancing | en |
dc.subject | Manycore | en |
dc.subject | Multitasking | en |
dc.subject | Clock speed | en |
dc.subject | Distributed Memory | en |
dc.subject | Execution context | en |
dc.subject | Execution framework | en |
dc.subject | Load-Balancing | en |
dc.subject | Many-core | en |
dc.subject | On chips | en |
dc.subject | Parallel processor | en |
dc.subject | Pipelined computation | en |
dc.subject | Processor cores | en |
dc.subject | Proof of concept | en |
dc.subject | Re-configurable | en |
dc.subject | Runtimes | en |
dc.subject | Soft processors | en |
dc.subject | Software support | en |
dc.subject | Computer architecture | en |
dc.subject | Dynamic loads | en |
dc.subject | Dynamic programming | en |
dc.subject | Program processors | en |
dc.subject | Pipeline processing systems | en |
dc.title | Supporting multitasking of pipelined computations on embedded parallel processor arrays | en |
dc.type | conferenceItem | en |
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