Sfoglia per Soggetto "Field programmable gate arrays (FPGA)"
Items 1-20 di 29
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Architectures for SLAM and augmented reality computing
(2021)In the next few years, new demanding applications will be supported on mobile platforms by reconciling two conflicting requirements: high performance (often with real-time limitations) and low power consumption. The objective ... -
Design Space Exploration of a Sparse MobileNetV2 Using High-Level Synthesis and Sparse Matrix Techniques on FPGAs
(2022)Convolution Neural Networks (CNNs) are gaining ground in deep learning and Artificial Intelligence (AI) domains, and they can benefit from rapid prototyping in order to produce efficient and low-power hardware designs. The ... -
Development of a SIPM based gamma-ray imager using a Gd3Al 2Ga3O12:Ce (GAGG:Ce) scintillator array
(2013)In this study we present the performance evaluation of a 6×6 Gd3Al2Ga3O12:Ce (GAGG:Ce) pixellated scintillator with 2×2×5mm 3 crystal size elements, coupled to a silicon photomultiplier array (ArraySL-4). Evaluation was ... -
An efficient implementation on a low cost FPGA for photon detection in nuclear imaging
(2010)The aim of this study is to propose and evaluate a simple, open source, data acquisition (DAQ) tool, which provides accurate results for nuclear imaging applications. For this purpose a Xilinx Spartan3E Starter Kit, which ... -
Enhancing design space exploration by extending CPU/GPU specifications onto FPGAs
(2015)The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of ... -
FPGA Architectures for Approximate Dense SLAM Computing
(2021)Simultaneous Localization and Mapping (SLAM) is the problem of constructing and continuously updating a map of an unknown environment while keeping track of an agent's trajectory within this environment. SLAM is widely ... -
A grammar induction method for clustering of operations in complex FPGA designs
(2014)In large-scale datapaths, complex interconnection requirements limit resource utilization and often dominate critical path delay. A variety of scheduling and binding algorithms have been proposed to reduce routing requirements ... -
High speed binary counter based on 1D Cellular Automata
(2016)This work presents a binary counter that was derived using the bASIC theory of 1D Cellular Automata. One of the 1D Cellular Automata seeds is producing an evolutionary structure in which the sequence of binary numbers is ... -
High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs
(2021)Ever since transistor cost stopped decreasing, customized programmable platforms, such as field-programmable gate arrays (FPGAs), became a major way to improve software execution performance and energy consumption. While ... -
A High-Performance Neuron for Artificial Neural Network based on Izhikevich model
(2019)Neuromorphic circuits have gained a lot of interest through the last decades since they may be deployed in a large spectrum of scientific research. In this paper a hardware realization of a single neuron targeting Field ... -
Implementation and performance analysis of SEAL encryption on FPGA, GPU and multi-core processors
(2011)Accelerators, such as field programmable gate arrays (FPGAs) and graphics processing units (GPUs), are special purpose processors designed to speed up compute-intensive sections of applications. FPGAs are highly customizable, ... -
Implementation and performance comparison of the motion compensation kernel of the AVS video decoder on FPGA, GPU and multicore processors
(2011)Next generation video standards have strict and increasing performance demands due to real-time requirements and the trend towards higher frame resolutions and bit rates. Leveraging the advantages of reconfigurable logic ... -
Juxtaposing Vivado Design Flows in Batch Mode
(2021)Re-configurable hardware devices are at the forefront of technological advancement and academic research, with their most prominent delegate being Field Programmable Gate Arrays (FPGAs). A typical FPGA design cycle may ... -
Massively parallel programming models used as hardware description languages: The OpenCL case
(2011)The problem of automatically generating hardware modules from high level application representations has been at the forefront of EDA research during the last few years. In this paper, we introduce a methodology to ... -
Multithreading on reconfigurable hardware: A performance evaluation approach of a multicore FPGA architecture
(2021)This paper addresses the performance issues of multiple threads running on a multithreaded field programmable gate array (FPGA) multicore architecture, supported by a realtime variant of Linux operating system. The objective ... -
On the characterization of OpenCL dwarfs on fixed and reconfigurable platforms
(2014)The proliferation of heterogeneous computing platforms presents the parallel computing community with new challenges. One such challenge entails evaluating the efficacy of such parallel architectures and identifying the ... -
On the portability of the OpenCL Dwarfs on fixed and reconfigurable parallel platforms
(2013)The proliferation of heterogeneous computing systems presents the parallel computing community with the challenge of porting legacy and emerging applications to multiple processors with diverse programming abstractions. ... -
OpenDwarfs: Characterization of Dwarf-Based Benchmarks on Fixed and Reconfigurable Architectures
(2016)The proliferation of heterogeneous computing platforms presents the parallel computing community with new challenges. One such challenge entails evaluating the efficacy of such parallel architectures and identifying the ... -
Optically-Enabled Bloom Filter Label Forwarding Using a Silicon Photonic Switching Matrix
(2017)Simplified forwarding schemes relying on Bloom filter (BF)-based labels emerge as a promising approach for coping with the substantial increase in lookup table memory requirements associated with the growing number of ... -
Parallelised Multithreaded Applications on a 4-core Field Programmable Gate Array (FPGA) Architecture
(2022)Background: The challenges in real-time multithreading, particularly in the efficiency of multithreaded applications running concurrently on multiple cores, have evolved significantly due to the increase in IoT, cloud and ...