Graph-Based STA for Asynchronous Controllers

Abstract

In this work, we present an Asynchronous Static Timing Analysis (ASTA) EDA methodology for cyclic, Asynchronous Control Circuits. Our methodology operates using Graph-based Analysis (GBA) principles, as conventional synchronous GBA STA, is fast, and pessimistically computes Critical Cycle(s), instead of Critical Paths, without cycle cutting. Our ASTA flow supports industrial Timing Libraries, Verilog input and multiple PVT corners. Gate timing arc delay/slew computation, input/output environment constraints, and path delay propagation, are implemented based on GBA STA principles. To perform ASTA, both gate-level netlist and a graph-based Event Model, Marked Graph (MG) or PeTri Net (PTnet), is required. The pair is used to construct the Event Timing Graph (ETG), an MG with annotated netlist extracted delays, for Event Model Transition to Transition (T2T) arcs. ETG delays are computed automatically, based on cyclic equilibrium slews, and GBA critical path identification between relevant T2T netlist gate pins. GBA T2T paths may be manually overridden. As GBA is non-functional, we illustrate a mapping between an Event Model, where choice places may be allowed, and the ETG, where places are collapsed to their corresponding timing annotated T2T arcs. The resultant ETG is live and 1-bounded, making it suitable for Period analysis using Burns Primal-Dual Algorithm. Our methodology has been successfully tested on 23 asynchronous benchmarks, and validated via timing simulation. We compare results against an industrial, synchronous STA tool with cycle cutting, and illustrate significant timing errors, when synchronous STA is used for delay annotation, as well as a 50% delta in Critical Cycle Delay. © 2019 IEEE.