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Near Data Processing Performance Improvement Prediction via Metric-Based Workload Classification

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Autor
Papalekas D., Tziouvaras A., Floros G., Dimitriou G., Dossis M., Stamoulis G.
Datum
2022
Language
en
DOI
10.1109/MOCAST54814.2022.9837704
Schlagwort
Cache memory
Data handling
Machine learning
Three dimensional integrated circuits
3D-stacked memory
Data-intensive application
Energy
Graph processing
Machine-learning
Near-data-processing
Performance bottlenecks
Processing algorithms
Processing performance
Processing-in-memory
Dynamic random access storage
Institute of Electrical and Electronics Engineers Inc.
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Zusammenfassung
Contrary to the improvement of CPU capabilities, traditional DRAM evolution faced significant challenges that render it the main performance bottleneck in contemporary systems. Data-Intensive applications such as Machine Learning and Graph Processing algorithms depend on time and energy consuming transactions between the memory bus and the CPU caches. The emergence of 3D-Stacked memories that provide a very high bandwidth led to the exploration of the Process-In-Memory (PIM) paradigm where logic is added to the memory die and data are being processed where they reside. To fully exploit this model, there is a need to methodically determine the portions of code that are better fitted for Near-Data-Processing (NDP). To this extend, in this work, after presenting the key trends of the research field and examine proposed criteria, we simplify the process of a priori decision of a block's suitability by proposing a two-step metric-based application categorization able to predict the applications behavior when offloaded for NDP. © 2022 IEEE.
URI
http://hdl.handle.net/11615/77750
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