Redesign, Extensibility & Evaluation of a Placement Utilities Toolset

Abstract

Placement is a step in the physical design associated with laying the cells of an integrated circuit in a designated area, so that timing, congestion, and utilization goals are met. Placement is a major step in physical design thus, applying optimization methods relies heavily on implementing processes from scratch or the reuse of code that has been previously tested in similar procedures. A modern placer needs to handle large amount of cells with different sizes and placement constraints. For both industry and academia, a toolset comprising widely used functionalities, can be extremely practical and reduce the development and testing cycle. In this paper we present the Bookshelf Format Parser, a management toolset for bookshelf formatted designs, accompanied by an extensive evaluation of its elaborate and versatile architecture. We evaluate the performance of the proposed toolset using benchmarks derived from actual designs. Numerical results depict the performance of the proposed approach in terms of execution time and memory consumption while a comparative assessment reveals the position of the paper in the relevant literature. © 2021 IEEE