Sfoglia per Soggetto "Computer architecture"
Items 1-20 di 34
-
5G-XHaul: A Novel Wireless-Optical SDN Transport Network to Support Joint 5G Backhaul and Fronthaul Services
(2019)The increased carrier bandwidth and the number of antenna elements expected in 5G networks require a redesign of the traditional IP-based backhaul and CPRI-based fronthaul interfaces used in 4G networks. We envision future ... -
Bayesian annealed sequential importance sampling: An unbiased version of transitional Markov chain Monte Carlo
(2018)The transitional Markov chain Monte Carlo (TMCMC) is one of the efficient algorithms for performing Markov chain Monte Carlo (MCMC) in the context of Bayesian uncertainty quantification in parallel computing architectures. ... -
Bayesian uncertainty quantification and propagation in molecular dynamics simulations
(2012)A comprehensive Bayesian probabilistic framework is developed for quantifying and calibrating the uncertainties in the parameters of the models (e.g. force-field potentials) involved in molecular dynamics (MD) simulations ... -
Cloud-based convergence of heterogeneous RANs in 5G disaggregated architectures
(2018)Cloud-RAN based architectures are widely considered a fundamental part of 5G networks. As a consequence, in the upcoming standards for 5G RAN, disaggregating the RAN functionality between a Central Unit (CU) and multiple ... -
Design architecture of a data driven environment for multiphysics applications
(2003)The design architecture of a multidisciplinary problem-solving environment (MPSE) for supporting an efficient prediction capability for the response of continuous interacting systems under multiphysics conditions is ... -
Distributed caching algorithms in the realm of layered video streaming
(2019)Distributed caching architectures have been proposed for bringing content close to requesters, and the key problem is to design caching algorithms for reducing content delivery delay, which determines to an extent the user ... -
Dynamic Undervolting to Improve Energy Efficiency on Multicore X86 CPUs
(2020)Chip manufacturers introduce redundancy at various levels of CPU design to guarantee correct operation, even for worst-case combinations of non-idealities in process variation and system operating conditions. This redundancy ... -
Exploiting task-based parallelism in Bayesian Uncertainty Quantification
(2015)We introduce a task-parallel framework for non-intrusive Bayesian Uncertainty Quantification and Propagation of complex and computationally demanding physical models on massively parallel computing architectures. The ... -
Fast dynamic binary rewriting for flexible thread migration on shared-ISA heterogeneous MPSoCs
(2014)Heterogeneous MPSoCs where different types of cores share a baseline ISA but implement different operational accelerators combine programmability with flexible customization. They hold promise for high performance under ... -
Fast dynamic binary rewriting to support thread migration in shared-ISA asymmetric multicores
(2013)Asymmetric multicore processors have demonstrated a strong potential for improving performance and energy-efficiency. Shared-ISA asymmetric multicore processors overcome pro- grammability problems in disjoint-ISA systems ... -
Federated Learning Protocols for IoT Edge Computing
(2022)In this article, we provide a set of federated learning (FL) protocols for future Internet architectures, which integrate the edge computing with the Internet of Things (IoT) known as 'IoT edge computing.' The proposed ... -
Forecasting of day-ahead natural gas consumption demand in Greece using adaptive neuro-fuzzy inference system
(2020)(1) Background: Forecasting of energy consumption demand is a crucial task linked directly with the economy of every country all over the world. Accurate natural gas consumption forecasting allows policy makers to formulate ... -
FPGA Architectures for Approximate Dense SLAM Computing
(2021)Simultaneous Localization and Mapping (SLAM) is the problem of constructing and continuously updating a map of an unknown environment while keeping track of an agent's trajectory within this environment. SLAM is widely ... -
A framework for MAC protocol misbehavior detection in wireless networks
(2005)The pervasiveness of wireless devices and the architectural organization of wireless networks in distributed communities, where no notion of trust can be assumed, are the main reasons for the growing interest in the issue ... -
HEVC decoder optimization in low power configurable architecture for wireless devices
(2015)High Efficiency Video Coding (HEVC) is the new video compression standard, reducing bitrates nearly at half compared to H.264, offering potentially significant power savings for wireless video transmission at the network ... -
Implementation and performance analysis of SEAL encryption on FPGA, GPU and multi-core processors
(2011)Accelerators, such as field programmable gate arrays (FPGAs) and graphics processing units (GPUs), are special purpose processors designed to speed up compute-intensive sections of applications. FPGAs are highly customizable, ... -
Implementation and performance comparison of the motion compensation kernel of the AVS video decoder on FPGA, GPU and multicore processors
(2011)Next generation video standards have strict and increasing performance demands due to real-time requirements and the trend towards higher frame resolutions and bit rates. Leveraging the advantages of reconfigurable logic ... -
Implementation experience in multi-domain SDN: Challenges, consolidation and future directions
(2017)Network architectures compliant with the Software Defined Networking (SDN) design paradigm, are expected to provide extreme flexibility for service orientation and allow for efficient use of network resources of cloud ... -
Loop scheduling for multithreaded processors
(2004)The presence of multiple active threads on the same processor can mask latency by rapid context switching, but it can adversely affect performance due to competition for shared datapath resources. In this paper we present ... -
Mapping and optimization of the AVS video decoder on a high performance chip multiprocessor
(2010)Modern multimedia workloads provide increased levels of quality and compression efficiency at the expense of substantially increased computational complexity. It is important to leverage the off-the-shelf emerging multi-core ...