• Presynthesis area estimation of reconfigurable streaming accelerators 

      Memik, S. O.; Bellas, N.; Mondal, S. (2008)
      In this paper, we propose algorithms for presynthesis estimation of hardware cost of a streaming accelerator. Our proposed estimation method helps to accelerate the design-spaceexploration phase by orders of magnitude by ...
    • A programmable Si-photonic node for SDN-enabled Bloom filter forwarding in disaggregated data centers 

      Moralis-Pegios M., Terzenidis N., Vagionas C., Pitris S., Chatzianagnostou E., Brimont A., Zanzi A., Sanchis P., Marti J., Kraft J., Rochracher K., Dorrestein S., Bogdan M., Tekin T., Syrivelis D., Tassiulas L., Miliou A., Pleros N., Vyrsokinos K. (2017)
      Programmable switching nodes supporting Software-Defined Networking (SDN) over optical interconnecting technologies arise as a key enabling technology for future disaggregated Data Center (DC) environments. The SDNenabling ...
    • A programming model and runtime system for approximation-aware heterogeneous computing 

      Parnassos I., Bellas N., Katsaros N., Patsiatzis N., Gkaras A., Kanellis K., Antonopoulos C.D., Spyrou M., Maroudas M. (2017)
      Heterogeneous platforms that include diverse architectures such as multicore CPUs, FPGAs and GPUs are becoming very popular due to their superior performance and energy efficiency. Besides heterogeneity, a promising approach ...
    • Scavenging PyPi for VLSI Packages 

      Kranas G.K., Dadaliaris A.N., Oikonomou P., Dossis M. (2022)
      Application Specific Integrated Circuits and Field Programmable Gate Arrays as well as their respective design flows have been the focus of many studies. As such the use of EDA tools becomes a necessity while researchers ...
    • Shortening design time through multiplatform simulations with a portable OpenCL golden-model: The LDPC decoder case 

      Falcao, G.; Owaida, M.; Novo, D.; Purnaprajna, M.; Bellas, N.; Antonopoulos, C. D.; Karakonstantis, G.; Burg, A.; Ienne, P. (2012)
      Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, ...
    • A SoC-ZYNQ-Based SW-HW Co-Simulation and Verification Method 

      Mahdi A.S., Archonta C., Tzimas G., El-Kady A. (2019)
      An architecture enabling a flexible on-board simulation and verification method for complex user-specific IPs is presented. The proposed method relies on an FPGA-SoC implementation of a golden simulation and verification ...
    • SoCLog: A real-time, automatically generated logging and profiling mechanism for FPGA-based Systems on Chip 

      Parnassos I., Skrimponis P., Zindros G., Bellas N. (2016)
      Recent advances in FPGA technology and the proliferation of High Level Synthesis (HLS) tools makes it possible to implement complex System on Chip (SoC) designs that realize complete applications in a single FPGA device. ...
    • A Sub-Sampling Approach for Data Acquisition in Gamma Ray Emission Tomography 

      Fysikopoulos E., Kopsinis Y., Georgiou M., Loudos G. (2016)
      State of the art data acquisition systems for small animal imaging gamma ray detectors often rely on free running Analog to Digital Converters (ADCs) and high density Field Programmable Gate Arrays (FPGA) devices for digital ...
    • Synthesis of platform architectures from OpenCL programs 

      Owaida, M.; Bellas, N.; Daloukas, K.; Antonopoulos, C. D. (2011)
      The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this paper, we use OpenCL, an industry supported ...